1. Field of the Invention
Certain inventive aspects relate to a method for isolating structures within a semiconductor device with high topography. They also relate to a multi-gate device obtained via application of the method.
2. Description of the Related Technology
Topography is a crucial part of device processing. This holds even more for Multi-Gate devices, which are regarded as possible alternatives for classical CMOS devices in sub-45 nm technologies. The term ‘Multi-Gate device’ or ‘MuGFET’ refers to a family of devices known in literature as FinFETs, Tri-gate, Omega-gate, Pi-gate, etc. Multi-gate FETs have been proposed as an option for the extremely short FET as due to the gate geometry they have superior short-channel effect immunity and control over bulk devices in the sub-30 nm physical gate length regime.
In a FinFET the gate at least partially envelops the channel region, as opposed to the classic planar device where the gate electrode is formed in one plane on top of the channel region, which is part of the substrate. The FinFET further comprises the source and drain regions adjacent to the channel region.
Important issues in the fabrication of these devices are e.g. the patterning of 25 nm gates over high topography due to the fins. In MUGFETs the active area is patterned from a semiconductor layer as e.g. SOI (Silicon On Insulator) layer of the order of tens of nm thick or a GOI (Germanium On Insulator) layer or SiGe layer, and consists of source and drain connected by fins. Narrow fins are required to have a better short channel effect control: typically the physical width of the fin should be about half of the gate length. The channel width on the other hand is determined by the height of the fin: the higher the fin, the more current can flow from source to drain. Therefore the gate stack is deposited on a surface with an intrinsically high topography.
In order to achieve small active areas, an important issue is how to maintain proper control when the lines patterned on semiconductor material are etched to separate the various FinFETs on the wafer. For controlling the critical dimension it is best to use dense long lines. By critical dimension (CD) it is meant the dimension of the smallest geometrical feature (width of interconnect line, contacts, trenches, etc.) which can be formed during semiconductor device manufacturing using a given technology.
However, a problem with such dense long lines patterned on semiconductor material is that their width is locally difficult to control where an open area in the line is to be provided. Various solutions to the problem have been proposed, such as performing a double patterning in the resist (fin layer). This allows good control of the critical dimension as well as an easier gap control. However, it creates regions with high and low topography. Alternatively, a double patterning in a hard mask or a double patterning with a second etch can be envisaged.
Another difficulty is that the density of the high topography pattern influences the processing of the layers on top of the high topography layer. This renders the CD control on the next layers more difficult, because a CD difference can be seen above regions with different density. One solution used today is to place extra dummy features in the high topography layer in regions where there weren't any present. This solution is limited because these dummy features have to be placed at a sufficiently great distance away from the active devices so as not to influence their electrical behaviour. Another solution to mitigate the above-mentioned drawback, that can be used in conjunction with the use of dummy features, is to apply a poly etch-back step (gate layer). This is performed on top of the fins. This solution, however, is limited in the planarization capability and still differences may be present in regions with substantial pattern density differences.
As already mentioned one prefers to have narrow fins in order to better control the short channel effect. Moreover, they are advantageous in terms of space utilization. An interesting way to achieve these goals is by applying spacer defined fins. Typically spacer defined fins are obtained by using a sacrificial layer. When this sacrificial layer is etched, two narrow spacers remain. The spacer defined fins are described in detail, e.g., in (EP 1383166, U.S. Pat. No. 6,706,571-B).